« Architecture and design of integrated SOI reconfigurable RF Power Amplifiers for multi-standard terminals »
Thursday, November 19, 2015 at 10:30
Abstract : This work focuses on the study and integration of a reconfigurable multi-mode multi-band power amplifier (MMPA) supporting 2G/3G/4G at several frequency bands in SOI CMOS 130nm technology. Current hybrid MMPA modules take advantage of multiple technologies, in particular GaAs for power devices. This adds to the cost and complexity of radiofrequency front-end modules. The original solution presented in this thesis is a significant step toward the integration of MMPA compared to the state of the art and initial results illustrates the relevance of the proposed architecture. A study on PA efficiency under 3G / 4G modulated signals is also presented by comparing load and supply modulation PA architectures. First, the context and state of the art are presented. A design methodology based on the study of different operating classes is then presented, which allows pre-sizing of power cells and optimal load impedance determination for high efficiency reconfigurable PA design. The proposed PA design methodology led to the implementation of PA demonstrators integrated in SOI CMOS 130nm technology. The first demonstrator is a two stage reconfigurable MMPA operating from 700MHz to 900MHz and supporting saturated and linear modes. The power stage comprises two SOI LDMOS power cells that are activated according to the desired mode. Tunable matching networks based on switched capacitor arrays allow optimization of the MMPA performance according to the mode and band. The measured prototype delivers up to 35dBm of output power in saturated mode with more than 58% efficiency. In linear mode, the measured output power exceeds 30dBm with efficiency higher than 47%. Compared to initial simulations, some differences were observed. In particular, underestimation of losses associated with MOM capacitors and sub-optimal interconnections are the root cause of the observed discrepancies. The second demonstrator is a passive load modulation PA architecture. It includes a SOI LDMOS power cell and a tunable matching network made of high power binary weighted switched capacitor arrays. The tunable matching network allows presenting an optimal load trajectory to the PA in order to maximize its back-off efficiency. Measured efficiency enhancement is higher than 55% compared to a fixed load configuration for 7dB to 11dB power back-offs.
Members of jury : • M. Jean-Michel FOURNIER, Professeur à Grenoble INP - Supervisor • M. Jean-Daniel ARNOULD, Maître de Conférences à Grenoble INP -Co-Supervisor • M. Alexandre GIRY, Ingénieur de recherche au CEA LETI -Co-supervisor • M. Thierry PARRA, Professeur à l’Université Paul Sabatier à Toulouse -Rapporteur • M. Thierry TARIS, Professeur à l’INP Bordeaux -Rapporteur • M. Tuami LASRI, Professeur à l’Université de Lille 1 - Reviewer • M. Pierre VINCENT, Chef du service SCCI au CEA LETI - Guest • M. Jean-Christophe NANAN, Chef d’équipe design NPI -Toulouse - Guest
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Thesis prepared in the laboratory: UMR 5130-IMEP-LaHC (Institut de Microélectronique,Electromagnétisme,Photonique –Laboratoire Hyperfréquences et Caractérisation ), supervised by M. Jean-Michel FOURNIER, Professor at Grenoble INP (Supervisor) and M. Jean-Daniel ARNOULD, Assistant professor at Grenoble INP (Co-supervisor).