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PhD defense of Krishna PRADEEP

Published on March 25, 2019
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April 8, 2019 | Access map
Defense of the DOCTORAL thesis of Krishna PRADEEP, for the University  Grenoble Alpes , speciality  "NANO ELECTRONICS & NANO TECHNOLOGIES ", entitled:
Amphi M001- Phelma /MINATEC
3 rue parvis Louis Néel
38016 Grenoble cedex1

Characterization and Modelling of Device Level Variability in Advanced FD-SOI MOSFETs

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Monday, April 8th, 2019 at 10h30
 
Abstarct:
The “Moore’s Law” has defined the advancement of the semi-conductor industry for almost half a century. The device dimensions have reduced with each new technology node, and the design community and the market for the semiconductor have always followed this advancement of the industry and created applications which took better advantage of these new devices. But during the past decade, with the device dimensions approaching the fundamental limits imposed by the materials, the pace of this scaling down of device dimensions has decreased. While the technology struggled to keep alive the spirit of “Moore’s Law” using innovative techniques like 3-D integration and new device architectures, the market also evolved to start making specific demands on the devices, like low power, low leakage devices demanded by Internet of Things (IoT) applications and high performance devices demanded by 5-G and data centre applications. So the semiconductor industry has slowly moved away from being driven by technology advancement, and rather it is now being driven by applications.
Increasing power dissipation is an unavoidable outcome of the scaling process, while also targeting higher frequency applications. Historically, this issue has been handled by replacing the basic transistors (BJTs by MOSFETs), freezing the operation frequency in the system, lowering supply voltage, etc. The reduction of supply voltage is even more important for low power applications like in IoT, but this is limited by the device variability. Lowering the supply voltage implies reduced margin for the designers to handle the device variability. This calls for access to improved tools for the designers to predict the variability in the devices and evaluate its effect on the performance of their design and also for innovations in technology to reduce the variability in the devices. This thesis concentrates in the first part, and evaluates how the device variability can be accurately modelled and how its prediction can be included in the compact models used by the designers in their SPICE simulations.
At first, the thesis analyses the device variability in advanced FD-SOI transistors using direct measurements. In the spatial scale, depending on the distance between the two devices being considered, the variability can be classified into intra-die, inter-die, inter-wafer, inter-lot or even between different fabs. For the sake of simplicity all the variability within a single die can be grouped together as local variability, while others as global variability. Finally between two arbitrary devices, there will be contributions from both local and global variability, in which case it is easier to term it as the total variability.
Dedicated measurement strategies are developed using specialized test structures to directly evaluate the variability in different spatial scales using C-V and I-V characterisations. The effect of variability is first analysed on selected figure of merits (FOMs) and process parameters extracted from the C-V and I-V curves, for which parameter extraction methodologies are developed or existing methods are improved. This analysis helps identify the statistical distribution of the parameters and possible correlations between them.
Later, the whole bias dependent variability in the I-V and C-V curves are analysed. For this, a universal metric, which works irrespective of the spatial scale of the variability, is derived based on the previously reported mismatch analysis for local variability. This thesis extends this approach to global and total variability also. Analysing the whole curves ensures that one does not miss some critical information in some particular bias range, which would not appear in the selected FOMs.
A statistical modelling approach is used to model the observed variability and identify the sources of variations, in terms of the sensitivities to each source of variability given using a physical compact model like Leti-UTSOI. The compact model is first calibrated on the C-V and I-V curves at different bias conditions and geometries. The analysis of the FOMs and their correlations helped identify the missing dependencies in the compact model, and these were additionally included by making small modifications to the compact model. The model was independently verified to reproduce the trends of electrostatic parameters (like threshold voltage) to process parameters (like vertical thicknesses) and mobility behaviour. This calibrated model is used to calculate the sensitivities to different sources of variability. This approach is applied to the different types of variability, irrespective of the spatial scale of variability, geometry of the device considered or the bias conditions. A single set of pure physical sources of variability, including the vertical and lateral dimensions of the transistor, oxide trap density, gate work function and source/drain series resistance, have been identified which accounts for all the cases studied. It is verified that the modified Leti-UTSOI compact model with the identified and quantified sources of variability can easily reproduce the measured variability using simple Monte-Carlo simulations.
Finally, owing to the demands made by IoT applications on having low power, low leakage devices, the gate leakage in these devices is also analysed in detail, including its variability. A simple analytical model based on WKB approximation for tunneling across a potential barrier is developed, and verified on these devices. The variability of the gate current is also analysed in detail in both local and global scale. The same statistical modelling approach is used to analyse the variability and identify its sources. The sources are identified to be physical oxide thickness and the barrier height. The analysis of gate current variability, coupled with the C-V analyses, also enabled the segregation of the variability in the interface layer and high-k layer in the oxide stacks of the advanced transistors.
A very detailed analysis of the device variability in advanced FD-SOI transistors is undertaken in this thesis and a novel and unique characterisation and modelling methodology for the different types of variability is presented. The dominant sources of variability in the device behaviour, in terms of C-V and I-V and also in terms of parasitics (like gate leakage current) are identified and quantified. This work paves the way to a greater understanding of the device variability in FD-SOI transistors and can be easily adopted to improve the predictability of compact models implemented in commercial SPICE  simulators for device variability.

Jury members:
  • Gérard GHIBAUDO - Supervisor
  • Jean-Michel SALLESE - Rapporteur
  • Jean-Michel PORTAL - Rapporteur
  • Mireille MOUIS - Examiner

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Partenaires

Thesis prepared in the laboratory : UMR 5130 - Institut de Microélectronique, Electromagnétisme et Photonique -Laboratoire d'hyperfréquences et de caractérisation , supervised by  Gérard GHIBAUDO, supervisor and  Patrick SCHEER Co-supervisor.

Date of update March 25, 2019

French
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Chambéry site
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