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PHD Defense of Lama RAHHAL

Published on November 4, 2014
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November 6, 2014 | Access map
Defense of a doctoral thesis of Lama RAHHAL  for the University of Grenoble, speciality  Nanoelectronics and NanoTechnlologies (NEET) entitled :
PHELMA /MINATEC  Amphitheater M001
3 rue Parvis Louis Néel - Grenoble

"analysis and modeling of mismatch phenomena in advanced MOS transistors "

Thursday, November 06, 2014 at 10:30

Abstract:
For correct operation, certain analog and digital circuits, such as current mirrors or SRAM, require pairs of MOS transistors that are electrically identical. Real devices, however, suffer from random local variations in the electrical parameters, a problem referred to as mismatch. The aim of this thesis is to understand the physical causes of mismatch, to quantify this phenomenon, and to propose solutions that enable to reduce its effects. In this context, four major areas are treated. The first one focuses on the optimization of mismatch measurement methodologies. A new technique for the measurement of Vt and β mismatch and an ID mismatch model are proposed, analyzed and applied to experimental data for 28 nm Bulk and FD SOI technologies. The second area focuses on the characterization of different configurations of MOS transistors in order to propose design architectures that are optimized for certain applications. Specifically, the possibility of replacing LDEMOS with transistors in cascode configuration is analyzed. The third area focuses on the analysis and modeling of mismatch phenomena in advanced Bulk and SOI transistors. Three aspects are analyzed: 1) the impact of the introduction of germanium in P channel of 28nm BULK transistors; 2) the elimination of the metal gate contribution to Vt mismatch by using 20nm Gate-last Bulk technology; 3) a descriptive study of the principal contributions to Vt, β and ID mismatch in 28 and 14 nm FD SOI technologies. The last area treats the mismatch trends with transistor aging. NBTI stress tests were applied to PMOS 28nm FD SOI transistors. Models of the Vt and β mismatch trends as a function of the induced interface traps and fixed charges at the Si/SiO2 interface and in the oxide were developed and discussed.

Keywords : Mismatch, transistors MOS, Vt, β, ID, 28nm Bulk, 20nm Metal-Gate-Last, LDEMOS, cascode configuration, 28nm FD SOI, 14nm FDSOI, NBTI.


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Partenaires

Thesis prepared in the laboratory : UMR 5130 - IMEP-LAHC (Institut de Microélectronique, Electromagnétisme, Photonique – Laboratoire hyperfréquences et caractérisation)  and STMicroelectronics, supervised by  Gérard GHIBAUDO.

Date of update January 9, 2015

Contact

M.Gérard GHIBAUDO
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IMEP-LAHC
Grenoble site
Grenoble INP - Minatec : 3, Parvis Louis Néel - CS 50257 - 38016 Grenoble Cedex 1

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