Aller au menu Aller au contenu
Microelectronics, electromagnetism, photonics , microwave
< >

> Events > PhD-Defenses

PhD Defense of NIER Olivier

Published on December 9, 2015
A+Augmenter la taille du texteA-Réduire la taille du texteImprimer le documentEnvoyer cette page par mail Partagez cet article Facebook Twitter Linked In Google+ Viadeo
PhD Defense December 18, 2015 | Access map
Thesis defense of NIER Olivier for a DOCTORAL  thesis at the University of Grenoble entitled:
Amphi P 005 - Phelma Polygone
23 rue des Martyrs
38016 Grenoble Cedex 01

« Development of TCAD modeling for low field electronics transport and strain engineering in advanced Fully Depleted Silicon On Insulator (FDSOI) CMOS transistors"

Thursday,  December 18, 2015 at 14:00

Abstract :
It is well known that that CMOS performances improvements in advanced technologies are not simply due to device dimension scaling but also to the introduction of new technological “boosters” such as new transistors architectures (FDSOI, trigate), high-k dielectric gate stacks, stress engineering or new channel material (Ge, III-V).
To face all these technological challenges, Technology Computer Aided Design (TCAD) is a powerful tool to guide the development of advanced technologies but also to reduce time development and cost.

In this context, this PhD work aimed at improving the modeling for 28/14 and 10FDSOI technologies with a particular attention on mechanical strain impacts.

First of all, a review of the main models implemented in state of the art device simulators has been performed. The limitations and assumptions of these models are highlighted and developments of the in-house STMicroelectronics solver for low field transport has been discussed. Then, a “top down” approach has also been set-up. It consists in using advanced physical-based solvers as a reference for TCAD empirical models calibration. Simulation has been compared with experiments: calibrated TCAD reproduced accurately split-CV mobility measurements varying the temperature, the back bias, the Interfacial Layer (IL) thickness and the stress configuration. Finally, a description of the methodologies used during this thesis to model stress induced by the process flow is perfor
 med. Simulations have been compared to nanobeam diffraction (NBD) strain measurements. The last part deals with TCAD modeling of advanced CMOS devices for 28/14 and 10FDSOI technology development. Mechanical simulations have been performed to model the stress profile in transistors and several solutions to optimize the stress configuration in sSOI and SiGe-based devices have been investigated."

Members of  jury :
Pr. Gerard Ghibaudo, CNRS IMEP LAHC representing Grenoble university
Pr Christophe Jungemann, Aachen University, referee
Pr Christophe Delerue, CNRS IEMN, referee
Dr Denis Rideau, STM, co supervisor
Pr David Esseni, Univ. Udine, co supervisor ( Italy)
Pr Raphael Clerc, Unv. Jean Monnet, co supervisor
Dr Jean Charles Barbé, CEA LETI, invited

A+Augmenter la taille du texteA-Réduire la taille du texteImprimer le documentEnvoyer cette page par mail Partagez cet article Facebook Twitter Linked In Google+ Viadeo


Thesis prepared in the laboratory STMicroelectronics supervised by  Raphael Clerc, Denis Rideau,  David Esseni and  Jean- Charles Barbé.

Date of update December 9, 2015


Envoyer un mail
Grenoble site
Grenoble INP - Minatec : 3, Parvis Louis Néel - CS 50257 - 38016 Grenoble Cedex 1

Chambéry site
Université de Savoie - F73376 Le Bourget du Lac Cedex

  CNRS      Site Grenoble-INP       Université Grenoble Alpes (UGA)      Université Savoie Mont Blanc
Univ. Grenoble Alpes