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Séminar, December 8th 2011

Published on October 10, 2011
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Seminar December 8, 2011
from  1 to 2pm
Open to researchers from other laboratories
Room BELLEDONNE, Bat BCAI - IMEP-LAHC/MINATEC,
 3 rue parvis Louis Neel - 38109 Grenoble Cedex

"Challenges of ESD RF protections in advanced CMOS technologies" by Philippe GALY

Abstract:
The main purpose of this presentation is to discuss the challenge of RF ESD protections for the Advanced CMOS technologies. Today, it is well known that the ElectroStatic Discharge (ESD) protection is already a major challenge. This is due to the complexity of the technologies (High K metal Gate, sub-nanometric size, dual oxide...) and due to the complexity of System On Chip (SOC) (Mono-multi dice, multi powers, multi applications, multi balls ...). After a short introduction on the technology Roadmap and SOC complexity, the ESD constraints are introduced. At this step, the main accent will be done on the integration context challenge. Afterwards, the focus will be on RF constraints coupled with ESD protections. Some approaches, results and silicon implementations are presented and evaluated.

Philippe GALY is Senior Expert in micro-nano electronics at STMicrolectronics R&D Crolles France since 2005. He manages 4 groups in the Advanced Device Design & ESD Solutions (ADDES) team. Before, he was professor in engineer school during 10 years old. He has authored or co-authored more than 75 publications, 2 books and 20 patents. He holds a Ph.D. and H.D.R. (academic research supervisor).



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Date of update December 2, 2011

Contact

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Documents to download

French
IMEP-LAHC
Grenoble site
Grenoble INP - Minatec : 3, Parvis Louis Néel - CS 50257 - 38016 Grenoble Cedex 1

Chambéry site
Université de Savoie - F73376 Le Bourget du Lac Cedex
 


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