Defense of a doctoral thesis of Giulio TORRENTE, for the University of Grenoble Alpes , speciality "NANO ELECTRONICS & NANO TECHNOLOGIES, entitled:
Amphi M001 - Bâtiment M-RDC - Phelma/Minatec 3 rue parvis Louis Néel 38016 Grenoble cedex1 Phelma Minatec (Bâtiment M-RDC, Amphi M001), 3 Parvis Louis Neel Grenoble
«Investigation of degradation mechanisms and related performance concerns in 40nm NOR Flash memories»
Tuesday, July 11th, 2017 at 10:30
Abstract: Flash technology still represents the preferred storage memory in many portable consumers and computer applications. However, the conventional Flash cell is now facing technological barriers and needs to be optimized pushing its working condition to the intrinsic physical limit. Such an optimization has to be done mainly focusing on reliability concerns, i.e. data retention and endurance, since representing the main limiting factors of technology down-scaling. For this reason, several works dealt with data retention concerns analyzing, characterizing and modeling the Stress Induced Leakage Current (SILC) with the final aim of limiting or control such an issue. However, there is no work which accurately explored the overall cell evolution during Program/Erase (P/E) cycling from a microscopic physical standpoint, especially in NOR technology, whose intrinsic 2D degradation nature makes complex the modeling and the analysis of the combined aging mechanisms.
In this thesis, an in-depth investigation of P/E degradation mechanisms in 40nm NOR Flash technology issued from STMicroelectronics is conducted. With the help of advanced electrical characterization and proper TCAD simulation, this thesis provides an accurate understanding, evaluation and modeling of the different aging mechanisms involved during P/E cycling. In particular, the respective roles of Hot Carrier Degradation (HCD) and Fowler-Nordheim Stress (FNS) are pointed out, and their impact on memory cell characteristic drifts and on memory lifetime is assessed. The main challenge is to build a physically-based model which reproduces the Flash cell wear out during P/E cycling. This enables to push the memory lifetime towards its maximum intrinsic performance, as for example by correctly managing the P/E electrical operations. In addition, such an approach allows to assess the limiting physical mechanism factors for memory cell degradation and consequently to take action for some specific process step optimizations.
Members of jury :
- Mireille MOUIS, DR. CNRS Alpes : Examiner - Damien DELERUYELLE, PR. INSA de Lyon : Reviewer - Raphael CLERC, PR. Université de Saint Etienne : Reviewer - Gérard GHIBAUDO, DR. CNRS Alpes : Supervisor - David ROY, ING. STMicroelectronics : Co- supervisor, guest - Jean COIGNUS, ING. CEA-LETI : Co- supervisor, guest
A+Augmenter la taille du texteA-Réduire la taille du texteImprimer le documentTélécharger au format PDFEnvoyer cette page par mailPartagez cet articleFacebookTwitterLinked InGoogle+Viadeo
Thesis prepared at CEA supervised by Pr Gérard GHIBAUDO, DR. CNRS Alpes, and co-supervised by Charles LEROUX, ING. CEA-LETI.