Aller au menu Aller au contenu
Microelectronics, electromagnetism, photonics , microwave

> Events > Seminars

Exceptional seminar of Pr. Yuan TAUR

Published on September 5, 2016
A+Augmenter la taille du texteA-Réduire la taille du texteImprimer le documentEnvoyer cette page par mail cet article Facebook Twitter Linked In
Conference September 9, 2016 | Access map
Open to all : teachers, students, researchers, administrative, technicians

Amphi M001, PHELMA, Bât. INP, Minatec
3, parvis Louis Néel - 38000 Grenoble

“CMOS Device Scaling: Past, Present, and Future”

Friday, September 9th, 2016 from 10:00 to 11:30 am


CMOS technology ushered in the silicon VLSI era over thirty years ago. This talk reviews the history of CMOS devices and projects their future prospects. For any given technology node, CMOS performance is limited by the shortest channel length that can be made while maintaining the integrity of transistor action. The development of the MOSFET scale length theory will be tracked from the 1970s to the present, as it evolves from the one-region model for bulk MOSFETs, to the two-region model for dealing with thick, high- gate dielectrics, then to the three-region model for multiple-gate MOSFETs such as FinFETs. It gives powerful guidelines that, along with quantum mechanical considerations, allow the projection of scaling limits for bulk, SOI, double-gate, and nanowire MOSFETs.

Pr. Yuan TAUR received the B.S. degree in physics from National Taiwan University, Taipei, Taiwan, and the Ph.D. degree in physics from University of California, Berkeley.
From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. He has been appointed a Distinguished Professor in 2014.

Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He has authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book with Dr. Tak Ning of IBM, “Fundamentals of Modern VLSI Devices,” published by Cambridge University Press in 1998. The 2nd edition was published in 2009.
Dr. Yuan Taur received IEEE Electron Devices Society’s J. J. Ebers Award in 2012 “for contributions to the advancement of several generations of CMOS process technologies.” He also received IEEE Electron Devices Society’s Distinguished Service Award in 2014.

A+Augmenter la taille du texteA-Réduire la taille du texteImprimer le documentEnvoyer cette page par mail cet article Facebook Twitter Linked In


by Pr. Yuan TAUR

Date of update September 6, 2016

Grenoble site
Grenoble INP - Minatec : 3, Parvis Louis Néel - CS 50257 - 38016 Grenoble Cedex 1

Chambery site
Université Savoie Mont Blanc - Rue Lac de la Thuile, Bat. 21 - 73370 Le Bourget du Lac
  Logo CNRS_2019        Logo Grenoble INP - UGA   Grenoble Alps University    Université Savoie Mont Blanc
Université Grenoble Alpes