Defense of a doctoral thesis Sungjae CHANG for the University of Grenoble, speciality Nanoelectronics and NanoTechnlologies (NENT) intitled:
Amphithéatre M001 Phelma/ MINATEC/Grenoble-INP 3 rue Parvis Louis Néel - GRENOBLE
Characterization, mechanisms and memory applications of advanced SOI MOSFETs
Mr Sungjae CHANG
Monday 28th October 2013 at 14:00
Abstract: This thesis is dedicated to theoretical and experimental research on advanced SOI MOSFETs. Electrical characterization, modeling and simulations were carried out in order to investigate the device properties, physical mechanisms and appropriate applications. In ultrathin (5-10 nm) planar FD SOI device, the impact of temperature, back-gate bias and Si film thickness on the device performance is documented. Coupling effects are reported for a various range of fin width in vertical DG and triple-gate SOI FinFETs, via measurement and 3-dimensional simulation, with the aim of achieving dynamic threshold voltage modulation. Particular mobility behavior in ZnO thin film transistor is shown through low-temperature measurements. Adequate mobility models and parameter extraction techniques are proposed. High-field geometrical magnetoresistance measurements reveal the unusual, non universal behavior of carrier mobility in FD SOI and FinFETs. The second part of the manuscript is dedicated to innovative memory devices. In FinFETs fabricated on ONO buried insulator, nonvolatile charges can be stored in the nitride layer. We discuss the mechanisms of charge injection as well as the performance and advantages of this flash memory. A novel concept of unified memory and multi-bit volatile memory operation is demonstrated by combining flash and capacitorless memory operation. Systematical measurements reveal the impact of geometrical parameters, bias conditions and temperature on the nonvolatile and volatile memory effects.
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Thesis prepared in the laboratory IMEP-LAHC supervised by Mrs Maryline BADEWIN and Mr Sorin CRISTOLOVEANU