Modeling, simulation and electrical characterization of 1T-DRAM cell: A2RAM
Francois TCHEME WAKAM
Wednesday, December 18, 2019 at 10:30
The growth of transferring data, mainly due to applications such as Internet of Things, there is an increased need for storage system (memories). Ideally, we need a specific memory which would be integrated easily in all these applications. This memory must meet specific requirements such as : a simplicity of the operating mode, high density of integration, low power consumption, and low cost of manufacturing. A memory able to answer all these requirements does not exist, but a memory that is approaching these criteria is the embedded dynamic memory cell (DRAM) (eDRAM). DRAM has been proposed for the first time in 1968 in its traditional 1T / 1C-DRAM architecture. The transistor serves as an access point and the capacity is the storage point of the information. But, the main problem of this architecture is its low density of integration caused by the limitation of the scalability of its storage capacity. One solution could be the use of DRAM architectures without storage capacity : 1T-DRAM. In this case, the transistor is used to store and read information. Many DRAM 1T architectures can be found in the literature, but the aim of this PhD is to study the A2RAM through finite elements simulations (TCAD), electrical characterization and compact modeling to see if it can be used as embedded DRAM.
Jury members :
Gérard GHIBAUDO : Supervisor
Joris LACORD : Cosupervisor
Marylin BAWEDIN : Cosupervisor
Damien DELERUYELLE - Reviewer
Pascal MASSON - Reviewer
Philippe GALY - Examiner
Francis BALESTRA - Examiner
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Thesis prepared in the laboratory : CEA - CEA/LETI , supervised by Gérard GHIBAUDO, supervisor and Maryline BAWEDIN & Joris LACORD Cosupervisors.