Séminar, November 24th 2011

Abstract:
Within 10 years, transistors will have sub-10 nm channel length according to the ITRS reports. In addition, the gate dielectric materials will change from silicon dioxide to high-k materials to achieve a better of the gate control. Away from the planar structure, there are attempts to use three-dimensional (3-D) structures (e.g. multi-gate FETs) or 1-D nanowire structures (e.g. nanotubes and nanowires). These nano structured materials and devices are also good candidates for next-generation semiconductor devices.
In this presentation, the electrical transport and low-frequency noise properties from 3-D to 1-D structure devices such as FinFETs, junctionless FETs, nanowires, and graphene devices will be presented. Low-frequency noise has been useful to understand the carrier dynamics and can be a quality factor for nanostructured applications. From the view point of top-down and bottom-up approaches, the influence of channel conduction, device structure, strain technique, and metal contact is investigated.

Doyoung Jang received the B.S. and M.S. degrees in Electrical Engineering from Korea University (Seoul, Korea) in 2006 and 2008, respectively. He is currently working toward the Ph.D. degree in an international co-supervising program between the Nano Device Laboratory in Korea University, South Korea and IMEP-LAHC in Grenoble-INP, France. His research interests include the device physics and mainly low-frequency noise in quasi one-dimensional conductors such as FinFETs, Si/SiGe NWs, junctionless transistors, carbon nanotubes, and Graphene devices.