The « Ultimate CMOS » group has a 35 year experience in the design and characterization of semiconductor devices. In particular, it has been playing a pioneering role in the study and promotion of CMOS technologies on SOI. Our mission consists in exploring and expanding the frontiers of CMOS micro- and nano-electronics. The permanent objective is to unveil the physical mechanisms involved and their exploitation for the development of technologies, devices and their applications.
Our research activities are partly developed within the framework of the Labex MINOS
in Minatec, in strong link with our local partners
(CEA, ST, SOITEC
…) and international collaborators
(European networks of excellence, projects and bilateral agreements…). They are widely supported by European and national projects).New materials and new MOS architectures:
Being convinced that SOI and its variants are the key of future CMOS expansion and of the transition from micro to nanoelectronics, we are devoting much effort to this subject, both at the level of materials and devices. We are for instance studying alternative materials to bulk silicon such as SOI, GeOI, strained SiGe and III-V materials integrated on silicon, or wide bandgap materials. We are also studying the potential of new concepts and new architectures of transistors and memories. Steep subthreshold slope devices are for instance targeted for applications combining performance and low power consumption.Keywords: SOI, ultra-thin body and BOX (UTBB), GeOI, multiple gates, nanowire (NW), III-V MOSFET, Tunnel FET, steep slope, floating body effects, ReRAM, NVM, statistical and dynamic variability…Experimental analysis of electron transport and interfaces:
Our core expertise in characterization and parameter extraction is constantly solicited to transport properties and interface quality
for new materials (used for channel, gate of buried oxide) or to study the influence of mechanical engineering
and of device architecture
(ultra-thin films, multiple gates, FinFETs, JLTs, nanowires, etc.). It is important to note that the conclusions about the suitability of a given material should always be driven for short channels
typical of the envisioned technology nodes as they can be dramatically different from what is found for long channels!Keywords: electron and hole mobility, electron and hole velocity, saturation velocity, thermal velocity, out-of-equilibrium transport, scattering mechanisms, ballistic transport, quantum confinement, quantum coupling, front/back channel coupling, volume inversion, interface traps, defects…Characterization techniques and parameter extraction methodologies:
Understanding device physics requires that physically sounded parameters that are relevant to the mechanisms involved (such as electrostatic coupling, out-of-equilibrium and ballistic electron transport, scattering mechanisms, trapping/detrapping, or quantum effects) can be extracted from electrical characteristics (DC, small signal, transient or noise characteristics). To maintain our expertise at the best level, we are constantly developing our characterization techniques, the compact physical models that support our extraction methodologies as well as our simulation tools.Keywords: pseudo-MOS, Y-function, split CV, G-? analysis, transient analysis, Hall measurements, channel magnetoresistance, charge pumping, low frequency noise (LFN), low temperature measurements…Alternative technologies:
While this expertise has been initially been developed for CMOS, we are using it as well for the study of alternative technologies to silicon, which are presently attracting much attention, such as devices on wide bandgap materials (SiC, GaN), organic substrates or 2D materials.